Amorphous silicon has been used extensively in solar cells and display applications for a number of years. More recently, a new field of electronics has been growing, based upon the formation of large area circuits of amorphous silicon material upon large, inexpensive, transparent, glass substrates. The enabling technology is the ability to deposit thin films of this semiconducting material over large areas and the processing of circuits using techniques similar to conventional IC processing. Examples of such large area electronics are to be found described in U.S. Pat No. 4,584,592 entitled "Marking Head for Fluid Jet Assisted Ion Projection Imaging Systems", and U.S. Pat. No. 4,588,997 entitled "Electrographic Writing Head", both in the names of H. C. Tuan and M. J. Thompson, and assigned to the same assignee as the present invention. In both of these patents there is taught a large area marking head array including a large number of input or output transducers connected through thin film transistor (TFT) switches to a relatively small number of external array driver lines, all fabricated upon a single, large area substrate.
Although the amorphous silicon TFTs have met with considerable success in their applications, their extremely low carrier mobilities (typically below 1 cm.sup.2 /V-s) have limited their current driving capacity and ultimately device operating speed. On the other hand, polycrystalline silicon TFTs are expected to achieve higher carrier mobility, on the order of 20 to 100 cm.sup.2 /V-s and perhaps even higher speeds. From the perspective of device operating speed, this material would appear to present an attractive replacement for amorphous silicon in many applications.
A shortcoming of as-deposited polycrystalline films is their usual small grains which adversely effect carrier mobility. It is known that increasing grain size so as to reduce the number and detrimental effect of grain boundaries in the film will increase carrier mobility and enhance device performance. Usually grain size enhancement has required high temperature processing (&gt;1000.degree. C.) which would not be satisfactory for large area electronic arrays upon the desirable, low cost, glass substrates. For example, Corning 7059.RTM. is a good, inexpensive, mass produced glass having a high degree of flatness, whose anneal point is 630.degree. C. It would not be prudent for any processing thereon to exceed 600.degree. C. for an extended period of time. Recently the literature has included lower temperature techniques for enlarging grains in polycrystalline silicon thin films. The following two papers are representative of the current state of this art: "Low Temperature Polysilicon Super Thin-Film Transistor (LSFT)" by Noguchi et al, published in Japanese Journal of Applied Physics, Part 2 Letters, Vol. 25, No. 2, February 1986 at pp L121-L123 and "Comparison of Thin Film Transistors Fabricated at Low Temperatures (&lt;600.degree. C.) on As-Deposited and Amorphized-Crystallized Polycrystalline Si" by Kung et al, published in Journal of Applied Physics 61(4), Feb. 15, 1987 at pp 1638-1642.
The methods described in both of the above-identified papers include amorphizing the polycrystalline film by silicon ion implantation and subsequently recrystallizing the film with a low temperature (&lt;600.degree. C.) anneal. It is reported in the Noguchi et al article that the ion implantation energy is peaked at about the mid-film depth but the location of the implantation energy peak is not discussed in the Kung et al article. In both of the described methods, the effect of ion implantation is to destroy the crystalline lattice structures so as to convert the polycrystalline film to an amorphous form. By selecting the proper ion implantation angle, relative to normal incidence, the implantation will amorphize most of the crystalline grains in the film. Those random crystallites which were aligned with the ion beam will survive and will grow during the subsequent annealing step. Since the density of the surviving crystallites is greatly diminished, each will grow virtually unimpeded and will continue to enlarge until it meets a neighboring grain.
In each of the aforementioned references, the starting material has been a polycrystalline silicon film which has been nearly completely amorphized by ion implantation. The technique of amorphizing and recrystallizing a semiconductor layer, utilizing ion implantation also has been disclosed in the following patents: U.S. Pat. No. 4,463,492 (Maeguchi); U.S. Pat. No. 4,509,990 (Vasudev); and U.S. Pat. No. 4,588,447. It should be understood that the ion implantation step of this known technique results in a film having a predetermined number of grain growth sites.
We have found that it is desirable to use amorphous silicon as a starting material because of its absence of grain growth sites, its lower deposition temperature, compatible with low cost glasses, and its extremely smooth, as-deposited, surface which is a factor in increasing carrier mobility across device channel regions fabricated in the film. Therefore, an object of our invention is to provide a low temperature method for fabricating device grade, large grain, thin film polycrystalline silicon films upon a low cost, insulating, glass substrate. It is another object of this invention to process an amorphous silicon film so as to retard nucleation and cause it to occur randomly from the bottom surface of the amorphous film during a subsequent thermal annealing step, for allowing more extended grain growth.